1. Field of the Invention
The present invention generally relates to semiconductor devices, and particularly relates to a semiconductor device such as a DDR-SDRAM (double-data-rate synchronous dynamic random access memory) which latches input signals in synchronization with rising edges and falling edges of a data-strobe signal.
2. Description of the Related Art
FIG. 1 is a circuit diagram showing an example of a data-input circuit provided in a related-art DDR-SDRAM. In FIG. 1, a data-strobe-signal input terminal 1, a data-signal input terminal 2, and a reference-voltage input terminal 3 are shown.
An input circuit 4 for receiving a data strobe signal DQS includes a current-mirror-type differential amplifier 5, NMOS transistors 6 through 8, PMOS transistors 9 and 10, and inverters 11 and 12 for improving waveforms of the output signal of the current-mirror-type differential amplifier 5.
A latch-signal-generation circuit 13 includes inverters 14 through 16 for generating a latch signal SA by delaying and inverting the output signal of the input circuit 4, and further includes inverters 17 and 18 for generating a latch signal SB by delaying the output signal of the input circuit 4.
An input circuit 19 for receiving an input-data signal DQ includes a current-mirror-type differential amplifier 20, NMOS transistors 21 through 23, PMOS transistors 24 and 25, and inverters 26 and 27 for improving waveforms of the output signal of the current-mirror-type differential amplifier 20.
Further, a delay circuit 28 serves as a latch-target-signal generation circuit for generating a latch-target signal SC to be latched by delaying and inverting the output signal of the input circuit 19 so as to generate a delayed version of the input data signal DQ, and includes inverters 29 through 31.
A latch circuit 32 is a synchronous flip-flop circuit, and latches the latch-target signal SC in synchronization with rising edges of the latch signal SA. A latch circuit 33 is a synchronous flip-flop circuit, and latches the latch-target signal SC in synchronization with rising edges of the latch signal SB.
FIG. 2 is a timing chart showing operation of the data-input circuit of FIG. 1. FIG. 2 shows the data-strobe signal DQS input to the input circuit 4, the input-data signal DQ supplied to the input circuit 19, the latch signal SA, the latch signal SB, and the latch-target signal SC.
The related-art DDR-SDRAM shown in FIG. 1 is provided with the two latch circuits 32 and 33. The latch circuit 32 latches the latch-target signal SC in synchronization with the rising edges of the latch signal SA so as to latches the input-data signal DQ at rising edge timings of the data-strobe signal DQS (i.e., at phase positions having a 0 phase in the data-strobe signal DQS). The latch circuit 33 latches the latch-target signal SC in synchronization with the rising edges of the latch signal SB so as to latches the input-data signal DQ at falling edge timings of the data-strobe signal DQS (i.e., at phase positions having a 180 phase in the data-strobe signal DQS).
The latch signal SA is a signal that is obtained by delaying the data-strobe signal DQS by a total delay time ta of all the inverters 14 through 16 and the input circuit 4. The latch signal SB is a signal that is obtained by delaying the data-strobe signal DQS by a total delay time tb of all the inverters 17 and 18 and the input circuit 4. Further, the latch-target signal SC is a delayed version of the input-data signal DQ input to the input circuit 19 where the delay is equal to a total delay time tc of all the input circuit 19 and the delay circuit 28 combined.
In order to improve margins of a setup time tDS and a hold time tDH, which need to be defined with respect to the input-data signal DQ, it is preferable to achieve the conditions of ta=tb. In the related-art DDR-SDRAM shown in FIG. 1, however, there is no way to adjust the delay times ta and tb, except for adjusting a ratio of the charge-supply capacity (pull-up power) to the charge-discharge capacity (pull-down power) of the inverters 14 through 18.
Such adjustment of a ratio of the charge-supply capacity to the charge-discharge capacity of the inverters 14 through 18 can achieve the conditions of ta=tb only under specific circumstances regarding power-supply voltages, temperature, variation due to manufacturing process, etc. Namely, such adjustment cannot achieve the desired condition in a stable manner. In the related-art DDR-SDRAM shown in FIG. 1, therefore, it is almost impossible to improve margins of the setup time tDS and the hold time tDH that ought to be defined with respect to the input-data signal DQ. This hinders an effort toward faster operation speed.
Accordingly, there is a need for a semiconductor circuit that can improve margins of a setup time and a hold time defined with respect to an input signal that is latched at a double data rate, thereby helping efforts toward faster operation speed.